Assembly Syntax

Operands

The following operand syntax types are used in instructions

GPR operands

A GPR operand is written as r followed by the index number of the register.

Shifted GPR

A Shifted GPR operand is written as GPR << ABSIMM5.

A shifted GPR operand produces two variables. The Operand Specification is written as <GPR> << <ABS>

Invertible GPRs

An invertible GPR is written as either GPR (non-inverted) or ~GPR (inverted). An IGPR produces two variables. The Operand Specification is written as <INV> <GPR>.

A Shifted invertible GPR operand is written the same as GPR << ABSIMM5, except that GPR may be inverted. An SIGPR produces three variables, written as <INV> <GPR> << <ABS>

I/O Register Operand

An I/O Register Operand is written as io followed by the index number of the register.

Any Register

A Register in any map is either a GPR operand, and I/O Register operand, a system configuration register, a system information register, or a coprocessor register.

An interrupt register may be written as intrN or an alias name. Registers 1-3 may be written as intretN, Registers 4-7 are written intdN where N=r%4, Registers 8-11 are written intsN where N=r%4.

A system information register is written as info followed by the index number of the register.

A coprocessor register is written as co followed by the coprocessor number between 0 and 3, followed by r, followed by the register number. If the Assembler is aware of the particular coprocessor expected in a given coprocessor slot, it may use the alias name provided by the Coprocessor's Assembly Supplement. For example, if the Assembler is aware of the presence of a FPU (according to <float-coproc.md>) in slot 0, it may alias f0 as co0r0.

Immediates

Immediate operands take an integer or a symbol. n-bit Unsigned Immediates require an unsigned quantity in [0,2^n). Signed Immediates require a signed quantity in [-2^(n-1), 2^(n-1)).

Other than Absolute Immediates (like ABSIMM6), immediate operands can have symbols. Unless specified with the @pcrel modifier, Immediate operands always treat symbols as absolute address in relocations. The relocation requires that the address fits in the specified size of immediate (a link error occurs if it does not). using the special modifiers HI and LO allows you to instead specify the lower or upper 16-bits of the symbol.

Unless modified, immediate relocations uses (given the appropriate n):

• R_MICRON_<n>
• R_MICRON_LO16 (LO <sym>)
• R_MICRON_HI16 (HI <sym>)

With the @pcrel modifier (or for PCREL16, see below), the relocation uses (given the appropriate n):

• R_MICRON_PC16
• R_MICRON_LOPC16 (LO <sym>@pcrel)
• R_MICRON_HIPC16 (HI <sym>@pcrel)

Offsets

The PCREL16 and OFF15 values are special cases of immediates. PCREL16 is identical to a SIMM16 relocation, except that it defaults to resolving the specified symbol using a pc-relative relocation.

OFF15 is a 15-bit immediate that resolves a 17-bit pc-relative relocation or a 17-bit signed integer offset, and discards the lower two bits to encode the instruction. It has two constraints, in addition to the constraints that would apply to a 22-bit signed immediate:

• Absolute Expressions must be divisible by 4, and
• Relocation Expressions must produce a 4-byte aligned quantity. The Assembler may error if a misalignment is reliably detected (for example, a 3-byte offset from a symbol known to be 4-byte aligned).

OFF15 uses R_MICRON_JMPOFF relocation.

Sizes/Widths

A size or width expression is an absolute immediate that encodes a size (in bytes) or a width (in bits).

A BITW operand is a 5-bit unsigned absolute immediate that can take on any value between 1 and 32. 32 is encoded as 0. As a special case, the following synthetic constants are defined for BITW operands with the following values:

• byte: 8
• half: 16
• word: 32.

A BYTESZ operand is a 2-bit immediate with a special encoding of lg(sz) where sz is the real size in bytes. The value must be a power of 2 less than 8. The same synthetic constants are defined above to be 1, 2, and 4 respectively.

Interrupt Priorities

An interrupt priority is a priority level for the IRET instruction. It may be written as an ABSIMM2 or one of the following keywords. A value of 0 assembles, but is an illegal instruction at runtime.

• trap: 1
• async: 2
• irq: 3

Condition Code

Condition Codes appear only in mnemonics, and use the following 1 or 2 character short forms:

Instruction Syntax

The following charts describes how assemblers should interpret and assemble given instruction syntax forms and mnemonics.

Each Chart has the following information:

• Mnemonic: The name of the instruction, which should be interpreted case-insentively. The special variables <c> and <x> may be written here. c is as if defined CC <c> and x is as if defined ABSIMM2 <x>.
• Operands: A list of operands written as the Short ID followed by a variable in <> (e.g. GPR <d>)
• Opcode: The Opcode of the instruction. This may reference the special variable x if defined in the Mnemonic.
• Special Payload Encoding: A list of variable assignments of the form <var>=<val> where var is an encoding variable defined for the opcode in the ISA Spec, and val is either an integer expression or a variable. Implicitly the name of each encoding variable that is defined as a syntax variable in the Mnemonic or the Operands list is assigned to the value of that syntax variable. The special encoding variable P refers to the entire 24-bit payload (where its contents are undefined/ignored)
• Canonical: Describes whether or not the instruction specification is canonical Canonical Specifications are the primary (or only) way to describe a particular encoding (without a .instr directive). Non-canonical encodings may describe a more efficient way to write or read a particular encoding, or may be useful in niche circumstances. Disassemblers and machine-code generators (such as assembly printing from a compiler) should prefer the canonical specification if it has no context otherwise.

UND

PAUSE

MOV

LD/ST

Load/Add Immediates

Arithmetic Ops

Logic Ops

Shifts

Branches

I/O Transfers

Flags Manipulation

Exchange Register Contents

Extend Register Contents

Random Bit Generation

Coprocessor Invocations

Stop/Halt

Psuedo-instructions

Certain Menmonics assembly to a special sequence of instructions and to a link relaxation. These are expressed using macro assembly syntax, but are expected to be treated as intrinsics.

LDIW

.macro ldiw GPR <reg>, UIMM32 <val>
    ; Emits R_SKYARCH_RELAX16_32 if `val` is a symbol
    ldiu <reg>, <val>@LO
    addih <reg>, <val>@HI
.endmacro

.macro ldiw GPR <reg>, SIMM32 <val>
    ; Emits R_SKYARCH_RELAX16_32 if `val` is a symbol
    ldiu <reg>, <val>@LO
    addih <reg>, <val>@HI
.endmacro

May be converted to either ldi <reg>, <val> if the value is known to be in range

LRAW

Loads a wide relative address

.macro lraw GPR <reg>, PCREL32 <val>
    ; Emits R_SKYARCH_RELAX16_PC32 if `val` is a symbol
    lrau <reg>, <val>@LO
    addih <reg>, <val>@HI
.endmacro

may be converted to lra <reg>, val if the value is known to be in range

JMPW/JLW/CALLW

.macro jl<cc>w GPR <link>, PCREL32 <val>, GPR <scratch>=r15
    ; Emits R_SKYARCH_RELAXJMPOFF_PC32 if `val` is a symbol
    lraw <scratch>, <val>
    jlr<cc> <link>, <scratch>
.endmacro

.macro jlw GPR <link>, PCREL32 <val>, GPR <scratch>=r15
    jlalw <link>, <val>, <scratch>
.endmacro

.macro jmp<cc>w PCREL32 <val>, GPR <scratch>=r15
    jl<cc>w r0, <val>, <scratch>
.endmacro

.macro jmpw PCREL32 <val>, GPR <scratch>=r15
    jlw r0, <val>, <scratch>
.endmacro

.macro callw PCREL32, GPR <scratch>=r15
    jlw r31, <val>, <scratch>
.endmacro

May be converted to jl<cc> (as appropriate) if val is known to be in range. The value of <scratch> after the psuedo-instruction completes is unspecified (may not have been modified, or may be loaded with any value).